----------------------------------------------------------------------
-- Top, Clock skew
-- James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	
entity clock_skew is
	generic(
        -- Units here are ns
        -- Assumptions:
        --   1. Tsr >= Tpr
        --   2. Tsl >= Tpl
        --   3. Tpi, Tpr, Tpl >= 0
        -- Note: delta may be less than or greater than zero
		Tpl:time:=3 ns;     -- combinational logic propagation delay
		Tsl:time:=8 ns;     -- combinational settling delay
		Tsr:time:=8 ns;     -- register settling delay
		Tpr:time:=1 ns;     -- register propagation delay
		Tpi:time:=2 ns;     -- interconnect propagation delay
      delta:time:=0 ns    -- skew (see below)
      -- t1 = output of combinational logic (CL1) begins to load
      -- in register (R1).
      -- t2 = CL2 begins to load in R2.
      -- Delay between these two is skew
      -- t2 = t1 + delta
      -- delta = t2 - t1
	);
end entity;

architecture clock_skew of clock_skew is

   signal R1, R2, R1in, R1out, C1out : unsigned(1 downto 0);
   signal C1, C1in : unsigned(1 downto 0);
   signal clk, clk_delta : std_logic;
begin
   process(clk, R1in)
      begin
         if clk='1' then -- add "clk'event and" for edge-sensitive
            R1 <= R1in;
         end if;
   end process;

   process(clk_delta, C1out)
       begin
           if clk_delta='1' then -- add "clk'event and" for edge-sensitive
              R2 <= C1out;
           end if;
   end process;

   clk_delta <= transport clk after delta;

   R1out(0) <= transport R1(0) after Tpr;
   R1out(1) <= transport R1(1) after Tsr;
   C1in <= transport R1out after Tpi;
   C1 <= not(C1in);
   C1out(0) <= transport C1(0) after Tpl;
   C1out(1) <= transport C1(1) after Tsl;  
    
end architecture;
